The fabrication of a nanowire field effect transistor (FET) with a gate conductor surrounding the nanowire channel (also known as a gate-all-around nanowire FET) includes suspension of the nanowires. Suspension of the nanowires allows for the gate conductor to cover all surfaces of the nanowires.
The fabrication of a gate-all-around nanowire FET typically includes the following steps: (1) definition of the nanowires between source and drain regions by patterning a silicon-on-insulator (SOI) layer; suspension of the nanowires by isotropic etching that undercuts the insulator on which the nanowires are resting, also undercutting the insulator at the edge of the source and drain region; a blanket and conformal deposition of the gate conductor that wraps around the suspended nanowires and also fills the undercut at the edge of the source and drain regions; and definition of the gate line which includes the etching of the gate line and removal of gate conductor material from all regions outside the gate line, including gate material deposited in the cavities at the edge of the source and drain regions.
While the nanowire FET includes doped portions of nanowire that contact the channel region and serve as source and drain regions of the device, planar FETs include planar channel, source, and drain regions.